This week on the IEEE Digital Parts and Packaging Expertise Convention, Intel unveiled that it’s creating new chip packaging know-how that may enable for larger processors for AI.
With Moore’s Legislation slowing down, makers of superior GPUs and different knowledge middle chips are having so as to add extra silicon space to their merchandise to maintain up with the relentless rise of AI’s computing wants. However the most dimension of a single silicon chip is fastened at round 800 sq. millimeters (with one exception), so that they’ve needed to flip to superior packaging applied sciences that combine a number of items of silicon in a method that lets them act like a single chip.
Three of the improvements Intel unveiled at ECTC had been aimed toward tackling limitations in simply how a lot silicon you possibly can squeeze right into a single package deal and the way massive that package deal will be. They embody enhancements to the know-how Intel makes use of to hyperlink adjoining silicon dies collectively, a extra correct methodology for bonding silicon to the package deal substrate, and system to develop the scale of a essential a part of the package deal that take away warmth. Collectively, the applied sciences allow the mixing of greater than 10,000 sq. millimeters of silicon inside a package deal that may be larger than 21,000 mm2—an enormous space concerning the dimension of 4 and a half bank cards.
EMIB will get a 3D improve
One of many limitations on how a lot silicon can slot in a single package deal has to do with connecting numerous silicon dies at their edges. Utilizing an natural polymer package deal substrate to interconnect the silicon dies is probably the most reasonably priced possibility, however a silicon substrate permits you to make extra dense connections at these edges.
Intel’s answer, launched greater than 5 years in the past, is to embed a small sliver of silicon within the natural package deal beneath the adjoining edges of the silicon dies. That sliver of silicon, known as EMIB, is etched with superb interconnects that improve the density of connections past what the natural substrate can deal with.
At ECTC, Intel unveiled the most recent twist on the EMIB know-how, known as EMIB-T. Along with the same old superb horizontal interconnects, EMIB-T offers comparatively thick vertical copper connections known as through-silicon vias, or TSVs. The TSVs enable energy from the circuit-board beneath to straight hook up with the chips above as a substitute of getting to route across the EMIB, decreasing energy misplaced by an extended journey. Moreover, EMIB-T accommodates a copper grid that acts as a floor aircraft to scale back noise within the energy delivered on account of course of cores and different circuits all of a sudden ramping up their workloads.
“It sounds easy, however this can be a know-how that brings loads of functionality to us,” says Rahul Manepalli, vp of substrate packaging know-how at Intel. With it and the opposite applied sciences Intel described, a buyer may join silicon equal to greater than 12 full dimension silicon dies—10,000 sq. millimeters of silicon—in a single package deal utilizing 38 or extra EMIB-T bridges.
Thermal management
One other know-how Intel reported at ECTC that helps improve the scale of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the know-how used right now to connect silicon dies to natural substrates. Micrometer-scale bumps of solder are positioned on the substrate the place they may hook up with a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the package deal’s interconnects to the silicon’s.
As a result of the silicon and the substrate develop at totally different charges when heated, engineers should restrict the inter-bump distance, or pitch. Moreover, the enlargement distinction makes it troublesome to reliably make very giant substrates stuffed with numerous silicon dies, which is the course AI processors have to go.
The brand new Intel tech makes the thermal enlargement mismatch extra predictable and manageable, says Manepalli. The result’s that very-large substrates will be populated with dies. Alternatively, the identical know-how can be utilized to extend the density of connections to EMIB all the way down to about one each 25 micrometers.
A flatter warmth spreader
These larger silicon assemblages will generate much more warmth than right now’s techniques. So it’s essential that the warmth’s pathway out of the silicon isn’t obstructed. An built-in piece of steel known as a warmth spreader is vital to that, however making one large enough for these giant packages is troublesome. The package deal substrate can warp and the steel warmth spreader itself won’t keep completely flat; so it won’t contact the tops of the recent dies it’s presupposed to be sucking the warmth from. Intel’s answer was to assemble the built-in warmth spreader in elements as a substitute of as one piece. This allowed it so as to add additional stiffening parts amongst different issues to maintain every part in flat and in place.
“Retaining it flat at increased temperatures is an enormous profit for reliability and yield,” says Manepalli.
Intel says the applied sciences are nonetheless within the in R&D stage and wouldn’t touch upon when these applied sciences would debut commercially. Nonetheless, they may doubtless should arrive within the subsequent few years for the Intel Foundry to compete with TSMC’s deliberate packaging enlargement.
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